1. Field of the Invention
The present invention relates to a method of fabricating a bipolar junction transistor (BJT), and in particular, a method of fabricating a self-aligned bipolar transistor.
2. Description of the Related Art
A bipolar transistor is an electronic device which simultaneously utilizes two carriers, i.e. electrons and holes, to conduct current. The structure of a bipolar transistor is a three terminal device formed from two closely connected pn junctions. The three terminals include an emitter, a base and a collector. However, in a common bipolar transistor, the emitter and the base are connected to a same material. An improvement with respect to current gain and emitter effectiveness is limited. In order to overcome the above drawbacks, a heterojunction bipolar transistor is utilized.
HBT refers to a bipolar transistor formed from a heterojunction. The so-called “heterojunction” refers to the utilization of a wider bandgap material for the emitter than that for the base. Further, in switch applications, HBT has the advantage of high current gain and extremely high cut-off frequency, and in microwave applications, HBT has the advantage of high power gain and high power density.
A typical manufacturing method for a bipolar junction transistor is described with reference to FIGS. 1A to 1E. FIGS. 1A through 1E are schematic, cross-sectional views showing a heterojunction bipolar transistor formed according to a conventional fabrication process.
As shown in FIG. 1A, a non-selective silicon-germanium (SiGe) epitaxial layer 102 is deposited over a substrate 100 that already comprises a collector terminal thereon. An insulation layer 104 is then deposited over the SiGe epitaxial layer 102.
In FIG. 1B, a part of the insulation layer 104 is removed by a photolithography and etching process to form an insulation layer 104a, and then, a polysilicon conductive layer 106 and an insulation layer 108 are sequentially formed on the substrate 100. Thereafter, a part of the insulation layer 108 and the polysilicon conductive layer 106 are removed by photolithography and etching process to expose an opening 110 of the insulation layer 104a. 
In FIG. 1C, a conformal insulation layer 112 is deposited over the substrate 100, and a spacer 114 is formed on the two sidewalls of the opening 110.
In FIG. 1D, the spacer 114 is utilized as a mask, and the insulation layer 112 within the opening 110 is removed by etching to expose the SiGe epitaxial layer 102. After that, a polysilicon conductive layer 116 is deposited over the substrate 100.
In FIG. 1E, a photolithography and etching method is used to define the polysilicon conductive layer 116, the insulation layer 112 and the insulation layer 108 to form the polysilicon conductive layer 116a, the insulation layer 112a and the insulation layer 108a. The polysilicon conductive layer 116a and the spacer 114 together form the emitter 116a of HBT and the polysilicon layer 106a form the base of HBT.
In the above fabrication process, several photolithography and etching process steps are required to form the emitter and the base for the HBT device, which would increase the cost of the device. Another problem is that the control limit of the lithography process would impact the device performance. For example, the window size of the emitter and the base would affect the current gain. Further, improper etching process would induce damages on the SiGe surface. Thus, a self-aligned HBT process is being developed to improve the aforementioned problems.
One prior art which deals with reducing the number of photolithography processes is described in U.S. Pat. No. 5,656,514 issued to Ahlgren et al. Ahlgren et al. use a self-aligned emitter implantation through an emitter opening window and rapid thermal annealing to obtain a high performance HBT. However, the process in forming the emitter opening window in the base opening is not a self-aligned process, and the positioning may or may not be critical. Further, an extrinsic base implant is not suitable for this method.
The U.S. Pat. No. 5,106,767 issued to Comfort et al. provides another process of fabricating a self-aligned heterojunction biopolar transistor using a non-selective epitaxy base and multi-dielectric layer to form a HBT structure. However, the process is complicated and might cause improper diffusion of the base impurity during oxidation.
In another prior art approach shown in U.S. Pat. No. 6,417,059B2 by Huang, Huang describes a process using an etch stop layer on the base area to protect the SiGe layer from being damaged during the etch process. However, this process is not a self-aligned process and the junction positioning is critical. Further, the etch stop layer on the extrinsic base layer would restrict the base electrode silicidation capability and cause a higher resistivity.